(a) Field of the Invention
The invention relates to electronic circuits, and more particularly, to latch inverters and flip-flops using the same.
(b) Description of the Related Art
FIG. 1A shows a typical double latch data flip-flop (DDFF) 10. A typical DDFF 10 receives two input signals D1 and D2, and two trigger clocks CLK1 and CLK2, to generate an output signal Dout. During the rising edge of the trigger clock CLK1, the state of the input signal D1 is selected as the state of the output signal Dout in the DDFF 10; while during the rising edge of the trigger clock CLK2, the state of the input signal D2 is selected as the state of the output signal Dout in the DDFF 10. Hence, two separate parallel data can be merged into one serial data output through the use of the DDFF 10.
FIG. 1B shows a circuit illustrating a conventional DDFF 10, which includes four latch inverters 111, 112, 113, 114, a buffer 12, and two latches 13, 13′. The first latch inverter 111 receives a first data signal D1 and a trigger clock CLK1, and generates a first latch signal DD1. As the voltage level of the trigger clock CLK1 is low, the voltage level of the first latch signal DD1 becomes the inverted voltage level of the D1. The third latch inverter 113 receives the first latch signal DD1 and the trigger clock CLK1, and generates a third trigger clock DD3. As the voltage level of the trigger clock CLK1 is high, the voltage level of the third trigger clock DD3 becomes the inverted voltage level of the first latch signal DD1, namely the voltage level of the first data signal D1. The operations of the second latch inverter 112 and the fourth latch inverter 114 are similar to those of the first latch inverter 111 and the third latch inverter 113, except that the trigger clock received by the second latch inverter 112 and the fourth latch inverter 114 is the trigger clocks CLk2. In common use, the trigger clock CLK2 is the inverted version of the trigger clock CLK1.
The latches 13 and 13′ are used to maintain the voltage levels of the first latch signal DD1 and the second latch signal DD2. The buffer 12 receives the third latch signal DD3 and the fourth latch signal DD4 and generates an output signal Dout.
Through the alternation of the falling edge and the rising edge of the trigger clock CLK1, the DDFF 10 may superpose the two data signals D1 and D2 and output the output signal Dout whose frequency value is doubled. The relation between the input and the output of the DDFF 10 is shown in FIG. 2.
FIG. 3 is a schematic view illustrating the phenomenon seen in the latch inverters during the rising edge of the output signal, where the latch inverter 111 is shown as an example. Referring to FIG. 3, a node A is defined between the drain of a first PMOS transistor P1 and the source of a second PMOS transistor P2. A node B is defined between the source of a first NMOS transistor N1 and the drain of the second NMOS transistor N2. In a first instance when the voltage level of the node B is 0 and the voltage level of the latch signal DD1 is to be changed from 0 to 1, both the node B and the latch signal DD1 need to be charged to voltage level 1 by the supply voltage. A dash line shown in FIG. 4 indicates this voltage level change of the latch signal DD1 in the latch inverter 111. On the other hand, in a second instance when the voltage level of the node B is 1 and the voltage level of the latch signal DD1 is to be changed from 0 to 1, only the latch signal DD1 needs to be charged to voltage level 1 by the supply voltage. A solid line shown in FIG. 4 indicates this voltage level change of the latch signal DD1 in the latch inverter 111. Therefore, the slew rate in the first instance is different from the slew rate in the second instance.
FIG. 5 is a schematic view illustrating a phenomenon seen in the latch inverters during the falling edge of the output signal, where the latch inverter 111 is shown as an example. The locations of the nodes A and B shown in FIG. 5 are the same as those shown in FIG. 3. In a third instance when the voltage level of the node A is 1 and the voltage level of the latch signal DD1 is to be changed from 1 to 0, both the node A and the latch signal DD1 need to be discharged to voltage level 0 by the second NMOS transistor N2. A dash line shown in FIG. 6 indicates this voltage level change of the latch signal DD1 in the latch inverter 111. On the other hand, in a fourth instance when the voltage level of the node A is 0 and the voltage level of the latch signal DD1 is to be changed from 1 to 0, only the latch signal DD1 needs to be discharged to voltage level 0 by the second NMOS transistor N2. A solid line shown in FIG. 6 indicates this voltage level change of the latch signal DD1 in the latch inverter 111. Therefore, the slew rate in the third instance is different from the slew rate in the fourth instance.
As shown above, for these latch inverters, the slew rate of the latch signals is different for different instances of state change. This may caused data jitter in the output signals Dout of the double latch data flip-flop 10, and worsen data transmission quality.